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FEATURES Dynamic Range: 88.5 dB Resolution: 0.375 dB On-Chip Data Latches +5 V Operation AD7111A Pin Compatible with AD7524 Low Power APPLICATIONS Audio Attenuators Sonar Systems Function Generators Digitally Controlled AGC System
LC2MOS LOGDAC Logarithmic D/A Converter AD7111/AD7111A
FUNCTIONAL BLOCK DIAGRAMS
VDD VIN R FB
AD7111
17-BIT DAC
I OUT AGND
17-BIT LATCH
DECODE LOGIC
The LOGDAC(R) AD7111/AD7111A are monolithic multiplying D/A converters featuring wide dynamic range in a small package. Both DACs can attenuate an analog input signal over the range 0 dB to 88.5 dB in 0.375 dB steps. They are available in 16-pin DIPs and SOIC packages. The AD7111 is also available in a 20-terminal LCCC package. The degree of attenuation across the DAC is determined by an 8-bit word applied to the onboard decode logic. This 8-bit word is decoded into a 17-bit word which is then applied to a 17-bit R-2R ladder. The very fine step resolution, which is available over the entire dynamic range, is due to the use of this 17-bit DAC. The AD7111/AD7111A are easily interfaced to a standard 8-bit MPU bus via an 8-bit data port and standard microprocessor control lines. The AD7111 WR input is edge triggered and requires a rising edge to load new data to the DAC. The AD7111A WR is level triggered to allow transparent operation of the latches, if required. It should also be noted that the AD7111A is exactly pin and function-compatible with the AD7524, an industry standard 8-bit multiplying DAC. This allows an easy upgrading of existing AD7524 designs which would benefit both from the wider dynamic range and the finer step resolution offered by the AD7111A. The AD7111/AD7111A are fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.
LOGDAC is a registered trademark of Analog Devices, Inc.
GENERAL DESCRIPTION
CONTROL LOGIC
8-BIT BUFFER
CS VDD
WR
D0 - D7
DGND
VIN
R FB
AD7111A
17-BIT DAC
I OUT AGND
17-BIT LATCH
DECODE LOGIC
CONTROL LOGIC
8-BIT BUFFER
CS
WR
D0 - D7
DGND
PRODUCT HIGHLIGHTS
1. Wide Dynamic Range: 0 dB to 88.5 dB attenuation range in 0.375 dB steps. 2. Small Package: The AD7111/AD7111A are available in 16-pin DIPs and SOIC packages. 3. Transparent Latch Operation: By tying the CS and WR inputs low, the DAC latches in the AD7111A can be made transparent. 4. Fast Microprocessor Interface: Data setup times of 25 ns and write pulse width of 57 ns make the AD7111A compatible with modern microprocessors.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD7111-ELECTRICAL CHARACTERISTICS
Parameter NOMINAL RESOLUTION ACCURACY RELATIVE TO 0 dB ATTENUATION 0.375 dB Steps: Accuracy 0.17 dB Monotonic 0.75 dB Steps: Accuracy 0.35 dB Monotonic 1.5 dB Steps: Accuracy 0.7 dB Monotonic 3.0 dB Steps: Accuracy 1.4 dB Monotonic 6.0 dB Steps: Accuracy 2.7 dB Monotonic GAIN ERROR VIN INPUT RESISTANCE RFB INPUT RESISTANCE DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) Input Leakage Current SWITCHING CHARACTERISTICS tCS tCH tWR tDS tDH tRFSH POWER SUPPLY VDD IDD
1
AD7111/AD7111A-SPECIFICATIONS V, V (V = +5
AD7111L/C/U Grades TA = +25 C TA = TMIN, TMAX 0.375 0.375 0.375
DD IN = -10 V dc, IOUT = AGND = DGND = O V output amplifier AD711 except where noted)
AD7111K/B/T Grades TA = +25 C TA = TMIN, TMAX 0.375
Units dB
Conditions/Comments
0 to 36 0 to 54 0 to 48 0 to 72 0 to 54 Full Range 0 to 66 Full Range 0 to 72 Full Range 0.1 9/11/15
0 to 36 0 to 54 0 to 42 0 to 66 0 to 48 0 to 78 0 to 54 Full Range 0 to 60 Full Range 0.15 9/11/15
0 to 30 0 to 48 0 to 42 0 to 72 0 to 42 0 to 85.5 0 to 60 Full Range 0 to 60 Full Range 0.15 7/11/18
0 to 30 0 to 48 0 to 36 0 to 60 0 to 42 0 to 72 0 to 48 Full Range 0 to 48 Full Range 0.20 7/11/18
dB min dB min dB min dB min dB min dB min dB min dB min dB min dB min dB max k min/typ/max k min/typ/max V min V max A max ns min ns min ns min ns min ns min s min V mA max A max
Guaranteed Attenuation Ranges for Specified Step Sizes
Full Range Is from 0 dB to 88.5 dB
9.3/11.5/15.7 9.3/11.5/15.7 2.4 0.8 1 0 0 350 175 10 3 +5 1 500 2.4 0.8 10 0 0 500 250 10 4.5 +5 4 1000
7.3/11.5/18.8 7.3/11.5/18.8 2.4 0.8 1 0 0 350 175 10 3 +5 1 500 2.4 0.8 10 0 0 500 250 10 4.5 +5 4 1000
Digital Inputs = V DD Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulse Width Data Valid to Write Setup Time Data Valid to Write Hold Time Refresh Time
Digital Inputs = VIL or VIH Digital Inputs = 0 V or V DD; See Figure 6
NOTE 1 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
These characteristics are included for design guidance only and are not subject to test. VDD = +5 V, VIN = -10 V dc except where noted, IOUT = AGND = DGND = O V, output amplifier AD711 except where noted.
Parameter DC Supply Rejection, Gain/VDD Propagation Delay Digital-to-Analog Glitch Impulse AD7111L/C/U Grades TA = +25 C TA = TMIN, TMAX 0.001 3.0 100 0.005 4.5 AD7111K/B/T Grades TA = +25 C TA = TMIN, TMAX Units 0.001 3.0 100 0.005 4.5 Conditions/Comments
AC PERFORMANCE CHARACTERISTICS
Output Capacitance, Pin 1 Input Capacitance, Pin 15 and Pin 16 Feedthrough at 1 kHz Total Harmonic Distortion Output Noise Voltage Density Digital Input Capacitance
185 7 -94 -91 70 7
185 7 -72 -91 70 7
185 7 -94 -91 70 7
185 7 -68 -91 70 7
dB per % max VDD = 10%, Input Code = 00000000 s max Full-Scale Change Measured from WR Going High, CS = 0 V nV secs typ Measured with AD843 as Output Amplifier for Code Transition 10000000 to 00000000 C1 of Figure 1 is 0 pF pF max pF max dB max dB typ VIN = 6 V rms at 1 kHz nV/Hz max Includes AD711 Amplifier Noise pF max
Specifications subject to change without notice.
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AD7111/AD7111A AD7111A-ELECTRICAL CHARACTERISTICS AD711 except where noted)
Parameter NOMINAL RESOLUTION ACCURACY RELATIVE TO 0 dB ATTENUATION 0.375 dB Steps: Accuracy 0.17 dB Monotonic 0.75 dB Steps: Accuracy 0.35 dB Monotonic 1.5 dB Steps: Accuracy 0.7 dB Monotonic 3.0 dB Steps: Accuracy 1.4 dB Monotonic 6.0 dB Steps: Accuracy 2.7 dB Monotonic GAIN ERROR VIN INPUT RESISTANCE RFB INPUT RESISTANCE DIGITAL INPUTS VIH (Input High Voltage) VIL (Input High Voltage) Input Leakage Current SWITCHING CHARACTERISTICS 1 tCS tCH tWR tDS tDH POWER SUPPLY VDD IDD AD7111AC Grade TA = +25 C TA = TMIN, TMAX 0.375 0.375 AD7111AB Grade TA = +25 C TA = TMIN, TMAX 0.375 0.375
(VDD = +5 V, VIN = -10 V dc, IOUT = AGND = DGND = O V output amplifier
Units dB
Conditions/Comments
0 to 36 0 to 54 0 to 48 0 to 72 0 to 54 Full Range 0 to 66 Full Range 0 to 72 Full Range 0.1 9/11/15
0 to 36 0 to 54 0 to 42 0 to 66 0 to 48 0 to 78 0 to 54 Full Range 0 to 60 Full Range 0.15 9/11/15
0 to 30 0 to 48 0 to 42 0 to 72 0 to 48 0 to 85.5 0 to 60 Full Range 0 to 60 Full Range 0.15 7/11/18
0 to 30 0 to 48 0 to 36 0 to 60 0 to 42 0 to 72 0 to 48 Full Range 0 to 48 Full Range 0.20 7/11/18
dB min dB min dB min dB min dB min dB min dB min dB min dB min dB min dB max k min/typ/max k min/typ/max V min V max A max ns min ns min ns min ns min ns min V mA max mA max
Guaranteed Attenuation Ranges for Specified Step Sizes
Full Range Is from 0 dB to 88.5 dB
9.3/11.5/15.7 9.3/11.5/15.7 2.4 0.8 1 0 0 57 25 10 +5 1 1 2.4 0.8 10 0 0 57 25 10 +5 2 1
7.3/11.5/18.8 7.3/11.5/18.8 2.4 0.8 1 0 0 57 25 10 +5 1 1 2.4 0.8 10 0 0 57 25 10 +5 2 1
Digital Inputs = V DD Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulse Width Data Valid to Write Setup Time Data Valid to Write Hold Time Digital Inputs = V IL or V IH CS = WR = 0 V Digital Inputs = 0 V or V DD; See Figure 6
NOTE 1 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
These characteristics are included for design guidance only and are not subject to test. VDD = +5 V, VIN = -10 V dc except where noted, IOUT = AGND = DGND = O V, output amplifier AD711 except where noted.
Parameter DC Supply Rejection, Gain/VDD Propagation Delay Digital-to-Analog Glitch Impulse AD7111AC Grade TA = +25 C TA = TMIN, TMAX 0.001 1 10 0.005 1.5 20 AD7111AB Grade TA = +25 C TA = TMIN, TMAX Units 0.001 1 10 0.005 1.5 20 Conditions/Comments
AC PERFORMANCE CHARACTERISTICS
Output Capacitance, Pin 1 Input Capacitance, Pin 15 and Pin 16 Feedthrough at 1 kHz Total Harmonic Distortion Output Noise Voltage Density Digital Input Capacitance
50 7 -94 -91 70 7
50 7 -90 -91 70 7
50 7 -92 -91 70 7
50 7 -90 -91 70 7
dB per % max VDD = 10%, Input Code = 00000000 s max Full-Scale Change Measured from WR Going High, CS = 0 V nV secs typ Measured with AD843 as Output Amplifier for Code Transition 10000000 to 00000000 C1 of Figure 1 is 0 pF pF max pF max dB max dB typ VIN = 6 V rms at 1 kHz nV/Hz max Includes AD711 Amplifier Noise pF max
Specifications subject to change without notice.
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AD7111/AD7111A
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
VDD (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VIN (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V IOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD VRFB to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD Power Dissipation, DIP . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117C/W Lead Temperature (Soldering, 10 secs) . . . . . . . . . +300C Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 1 W JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature (Soldering) Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
Power Dissipation, LCCC . . . . . . . . . . . . . . . . . . . . . . . . 1 W JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76C/W Lead Temperature (Soldering, 10 secs) . . . . . . . . . +300C Operating Temperature Range Commercial (K, L Versions) . . . . . . . . . . . . . 0C to +70C Industrial (B, C Versions) . . . . . . . . . . . . . -40C to +85C Extended (T, U Versions) . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7111/AD7111A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDES AD7111A ORDERING GUIDE
AD7111 ORDERING GUIDE
Model AD7111ABN AD7111ACN AD7111ABR AD7111ACR
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Specified Accuracy Range 0 dB to 60 dB 0 dB to 72 dB 0 dB to 60 dB 0 dB to 72 dB
Package Option1 N-16 N-16 R-16 R-16
Temperature Modell Range AD7111KN 0C to +70C AD7111BQ -40C to +85C AD7111LN 0C to +70C AD7111CQ -40C to +85C AD7111UQ/883B -55C to +125C AD7111TE/883B -55C to +125C
Specified Accuracy Range 0 dB to 60 dB 0 dB to 60 dB 0 dB to 72 dB 0 dB to 72 dB 0 dB to 72 dB 0 dB to 60 dB
Package Option2 N-16 Q-16 N-16 Q-16 Q-16 E-20A
NOTE 1 N = Plastic DIP; R = SOIC.
NOTES 1 To order MIL-STD-883B, Class B processed parts, add /883B to part number. Contact local sales office for military data sheet and availability. 2 N = Plastic DIP; Q = Cerdip; E = LCCC; R = SOIC.
TERMINOLOGY
RESOLUTION: Nominal change in attenuation when moving between two adjacent codes. MONOTONICITY: The device is monotonic if the analog output decreases (or remains constant) as the digital code increases. FEEDTHROUGH ERROR: That portion of the input signal which reaches the output when all digital inputs are high. See section on Applications. OUTPUT LEAKAGE CURRENT: Current which appears on the IOUT terminal with all digital inputs high. TOTAL HARMONIC DISTORTION: A measure of the harmonics introduced by the circuit when a pure sinusoid is applied to the input. It is expressed as the harmonic energy divided by the fundamental energy at the output.
ACCURACY: The difference (measured in dB) between the ideal transfer function as listed in Table I and the actual transfer function as measured with the device. OUTPUT CAPACITANCE: Capacitance from IOUT to ground. DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VIN = AGND. PROPAGATION DELAY: This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value.
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AD7111/AD7111A
PIN CONFIGURATIONS DIP/SOIC LCCC
Write Cycle Timing Diagram
CIRCUIT DESCRIPTION
GENERAL CIRCUIT DESCRIPTION The AD7111/AD7111A consists of a 17-bit R-2R CMOS multiplying D/A converter with extensive digital logic. The logic translates the 8-bit binary input into a 17-bit word which is used to drive the D/A converter. Input data on the D7-D0 bus is loaded into the input data latches using CS and WR control signals. When using the AD7111, the rising edge of WR latches the input data and initiates the internal data transfer to the decoder. A minimum time tRFSH, the refresh time, is required for the data to propagate through the decoder before a new data write is attempted. In contrast, the AD7111A WR input is level triggered to allow transparent operation of the latches if required. The transfer function for the circuit of Figure 1 is given by:
0. 375 N VO = -VIN 10 exp - 20
where 0.375 is the step size (resolution) in dB and N is the input code in decimal for values 0 to 239. For 240 N 255 the output is zero. Table I gives the output attenuation relative to 0 dB for all possible input codes.
Figure 1. Typical Circuit Configuration
or
VO VIN
dB = -0.375 N
The graphs on the last page give a pictorial representation of the specified accuracy and monotonic ranges for all grades of the AD7111/AD7111A. High attenuation levels are specified with less accuracy than low attenuation levels. The range of monotonic behavior depends upon the attenuation step size used.
Table I. Ideal Attenuation in dB vs. Input Code
D3-D0
D7-D4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0.0 6.0 12.0 18.0 24.0 30.0 36.0 42.0 48.0 54.0 60.0 66.0 72.0 78.0 84.0 MUTE 0001 0.375 6.375 12.375 18.375 24.375 30.375 36.375 42.375 48.375 54.375 60.375 66.375 72.375 78.375 84.375 MUTE 0010 0.75 6.75 12.75 18.75 24.75 30.75 36.75 42.75 48.75 54.75 60.75 66.75 72.75 78.75 84.75 MUTE 0011 1.125 7.125 13.125 19.125 25.125 31.125 37.125 43.125 49.125 55.125 61.125 67.125 73.125 79.125 85.125 MUTE 0100 1.5 7.5 13.5 19.5 25.5 31.5 37.5 43.5 49.5 55.5 61.5 67.5 73.5 79.5 85.5 MUTE 0101 1.875 7.875 13.875 19.875 25.875 31.875 37.875 43.875 49.875 55.875 61.875 67.875 73.875 79.875 85.875 MUTE 0110 2.25 8.25 14.25 20.25 26.25 32.25 38.25 44.25 50.25 56.25 62.25 68.25 74.25 80.25 86.25 MUTE 0111 2.625 8.625 14.625 20.625 26.625 32.625 38.625 44.625 50.625 56.625 62.625 68.625 74.625 80.625 86.625 MUTE 1000 3.0 9.0 15.0 21.0 27.0 33.0 39.0 45.0 51.0 57.0 63.0 69.0 75.0 81.0 87.0 MUTE 1001 3.375 9.375 15.375 21.375 27.375 33.375 39.375 45.375 51.375 57.375 63.375 69.375 75.375 81.375 87.375 MUTE 1010 3.75 9.75 15.75 21.75 27.75 33.75 39.75 45.75 51.75 57.75 63.75 69.75 75.75 81.75 87.75 MUTE 1011 4.125 10.125 16.125 22.125 28.125 34.125 40.125 46.125 52.125 58.125 64.125 70.125 76.125 82.125 88.125 MUTE 1100 4.5 10.5 16.5 22.5 28.5 34.5 40.5 46.5 52.5 58.5 64.5 70.5 76.5 82.5 88.5 MUTE 1101 4.875 10.875 16.875 22.875 28.875 34.875 40.875 46.875 52.875 58.875 64.875 70.875 76.875 82.875 88.875 MUTE 1110 5.25 11.25 17.25 23.25 29.25 35.25 41.25 47.25 53.25 59.25 65.25 71.25 77.25 83.25 89.25 MUTE 1111 5.625 11.625 17.625 23.625 29.625 35.625 41.625 47.625 53.625 59.625 65.625 71.625 77.625 83.625 89.625 MUTE
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AD7111/AD7111A
For example, the AD7111L is guaranteed monotonic in 0.375 dB steps from 0 dB to -54 dB inclusive and in 0.75 dB steps from 0 dB to -72 dB inclusive. To achieve monotonic operation over the entire 88.5 dB range it is necessary to select input codes so that the attenuation step size at any point is consistent with the step size guaranteed for monotonic operation at that point.
V OUT
A1
100 90
-0.2V
MSB DATA CHANGE C1 = 0pF
C1 = 15pF
10 0%
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the D/A converter section of the AD7111/AD7111A, and Figure 3 gives an approximate equivalent circuit. The current source ILEAKAGE is composed of surface and junction leakages. The resistor R0 as shown in Figure 3 is the equivalent output resistance of the device which varies with input code (excluding all 0s code) from 0.8R to 2R. R is typically 12 k. COUT is the capacitance due to the N channel switches and varies from about 20 pF to 50 pF depending upon the digital input. For further information on CMOS multiplying D/A converters, refer to "CMOS DAC Application Guide" which is available from Analog Devices, Publication Number G872b-8-1/89.
V OUT
5V 5V
200ns
DATA CHANGE FROM 80H TO 00H.
Figure 4. Response of AD7111/AD7111A with AD711
A1
100 90
0.4V
MSB DATA CHANGE C1 = 0pF
V OUT
10 0%
C1 = 15pF
V OUT
5V 5V 200ns
DATA CHANGE FROM 80H TO 00H.
Figure 5. Response of AD7111/AD7111A with 1/2 OP275
Figure 2. Simplified D/A Circuit of AD7111/AD7111A
In conventional CMOS D/A converter design, parasitic capacitance in N-channel D/A converter switches can give rise to glitches on the D/A converter output. These glitches result from digital feedthrough. The AD7111/AD7111A has been designed to minimize these glitches as much as possible. For operation beyond 250 kHz, capacitor C1 may be reduced in value. This gives an increase in bandwidth at the expense of a poorer transient response as shown in Figures 5 and 11. In circuits where C1 is not included, the high frequency roll-off point is primarily determined by the characteristics of the output amplifier and not the AD7111/AD7111A.
Figure 3. Equivalent Analog Output Circuit of AD7111/AD7111A
DYNAMIC PERFORMANCE
The dynamic performance of the AD7111/AD7111A will depend upon the gain and phase characteristics of the output amplifier, together with the optimum choice of PC board layout and decoupling components. Circuit layout is most important if the optimum performance of the AD7111/AD7111A is to be achieved. Most application problems stem from either poor layout, grounding errors, or inappropriate choice of amplifier. It is recommended that when using thc AD7111/AD7111A with a high speed amplifier, a capacitor (C1) he connected in the feedback path as shown in Figure 1. This capacitor, which should be between 10 pF and 30 pF, compensates for the phase lag introduced by the output capacitance of the D/A converter. Figures 4 and 5 show the performance of the AD7111/AD7111A using the AD711, a high speed, low cost BiFET amplifier, and the OP275, a dual, bipolar/JFET, audio amplifier. The performance without C1 is shown in the middle trace and the response with C1 in circuit shown in the bottom trace. -6-
Feedthrough and absolute accuracy are sensitive to output leakage current effects. For this reason it is recommended that the operating temperature of the AD7111/AD7111A be kept as close to 25C as is practically possible, particularly where the device's performance at high attenuation levels is important. A typical plot of leakage current vs. temperature is shown in Figure 10. Some solder fluxes and cleaning materials can form slightly conductive films which cause leakage effects between analog input and output. The user is cautioned to ensure that the manufacturing process for circuits using thc AD7111/AD7111A does not allow such films to form. Otherwise the feedthrough, accuracy and maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7111/AD7111A consists of a 17-bit R-2R type converter. To obtain optimum static performance at this level of resolution it is necessary to pay great attention to amplifier selection, circuit grounding, etc. Amplifier input has current results in a dc offset at the output of the amplifier due to the current flowing through the feedback resistor RFB. It is recommended that an amplifier with an input bias current of less than 10 nA be used (e.g., AD711) to minimize this offset. REV. 0
AD7111/AD7111A
Another error arises from the output amplifier s input offset voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7111/ AD7111A output impedance) varies as a function of attenuation level. This has the effect of varying thc "noise" gain of the amplifier, thus creating a varying error due to amplifier offset voltage. It is recommended that an amplifier with less than 50 V of input offset be used (such as the AD OP07 in dc applications. Amplifiers with higher offset voltage may cause audible "thumps" in ac applications due to dc output changes. The AD7111/AD7111A accuracy is specified and tested using only the internal feedback resistor. Any gain error (i.e., mismatch of RFB to the R-2R ladder) that may exist in the AD7111/AD7111A D/A converter circuit results in a constant attenuation error over the whole range. The AD7111/AD7111A accuracy is specified relative to 0 dB attenuation, hence "Gain" trim resistors--R1 and R2 in Figure 1--can be used to adjust VOUT = VIN precisely (i.e., 0 dB attenuation) with input code 00000000. The accuracy and monotonic range specifications of the AD7111/AD7111A are not affected in any way by this gain trim procedure. For the AD7111/AD7111A L/C/U grades, suitable values for R1 and R2 of Figure 1 are R1 = 500 , R2 = 180 ; for the K/B/T grades, suitable value are R1 = 1000 , R2 = 270 . For additional information on gain error the reader is referred to the "CMOS DAC Application Guide," available from Analog Devices, Inc., Publication Number G872b-8-1/89.
Typical Performance Characteristics
6 VDD = +5V 5 TA = +25C V IN APPLIED TO ALL DATA INPUTS CS = WR = 0V 4
1.0 V DD = +5V 0.5 TA = +85C
ERROR - dB
I DD - mA
3
0.0 TA = +25C
2
-0.5
1
0 0 1 2 3 INPUT VOLTAGE - Volts 4 5
-1.0 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 ATTENUATION - dB
Figure 6. Typical Supply Current vs. Logic Input Level
Figure 8. Typical Attenuation Error for 3 dB Steps vs. Temperature
0.4 VDD = +5V 0.2 TA = +25C
ERROR - dB
0.0
* *
*
*** * **
**
****** **
***
* *** * * ** * ** ** ** ** **
-0.2
-0.4
-0.6 0 3 6 9 12 15 18 21 24 27 30 ATTENUATION - dB
Figure 7. Typical Attenuation Error for 0.75 dB Steps
Figure 9. Accuracy Specification for K/B/T Grade Devices at TA = +25C
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AD7111/AD7111A-Typical Performance Characteristics
2.0
OUTPUT LEAKAGE CURRENT I OUT - nA
-60
TOTAL HARMONIC DISTORTION - dB
VDD = +5V VIN = -10V DATA INPUT = 1111XXXX
VIN = 6V rms INPUT CODE = 0000 0000 T = +25C A C1 = 15pF 1/2 OP- 275
1.5
-70
AD711
0.5
-90
0.0 -40
-100
-15 10 35 60 85 TEMPERATURE - C
101
10 2
10 3 FREQUENCY - Hz
10 4
10 5
Figure 10. Output Leakage Current vs. Temperature
Figure 12. Distortion vs. Frequency
10
NORMALIZED GAIN WITH RESPECT TO 1kHz
1/2 OP - 275 C1 = 0pF
0 1/2 OP - 275 C1 = 15pF -10 AD711 C1 = 0pF -20 V DD = +5V TA = +25C DATA INPUT CODE = 0000 0000 VIN = 1V rms
3 4 5
AD711 C1 = 15pF
-30 2 10
10
10 10 FREQUENCY - Hz
10
6
10
7
Figure 11. Frequency Response with 1/2 OP275 and AD711 Amplifiers
Figure 13. Accuracy Specification for L/C/U Grade Devices at TA = +25C
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-16)
SOIC (R-16)
Cerdip (Q-16)
LCCC (E-20A)
-8-
REV. 0
PRINTED IN U.S.A.
C1687-10-7/92
1.0
-80

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